<html>
<head><meta charset="utf-8"><title>Libre-SOC&#x27;s SimpleV · project-portable-simd · Zulip Chat Archive</title></head>
<h2>Stream: <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/index.html">project-portable-simd</a></h2>
<h3>Topic: <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Libre-SOC&#x27;s.20SimpleV.html">Libre-SOC&#x27;s SimpleV</a></h3>

<hr>

<base href="https://rust-lang.zulipchat.com">

<head><link href="https://rust-lang.github.io/zulip_archive/style.css" rel="stylesheet"></head>

<a name="211713135"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Libre-SOC%27s%20SimpleV/near/211713135" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jacob Lifshay <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Libre-SOC&#x27;s.20SimpleV.html#211713135">(Sep 30 2020 at 04:00)</a>:</h4>
<p>I'm one of the main designers for <a href="https://libre-soc.org/simple_v_extension/specification/">Libre-SOC's SimpleV</a> SIMD/Vectors ISA, which is designed to support both variable-length (like the RISC-V V extension) and fixed-length vectors with lengths of 0 to 64 (includes non-powers of 2). We're planning on implementing support in LLVM and probably also Cranelift. I figured it would be mutually beneficial to have dialogue on design between our respective open-source projects. Note that we are in-progress converting to basing the ISA on OpenPower (PowerPC) rather than RISC-V, so a lot of the documentation has not yet been updated to account for that.</p>
<p><a href="https://libre-soc.org/">Libre-SOC</a> is a project to build a Libre-licensed hybrid CPU/GPU with drivers for modern 3D graphics APIs that is currently mostly funded by NLNet. Everyone's welcome to help out!</p>



<a name="211713430"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Libre-SOC%27s%20SimpleV/near/211713430" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Lokathor <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Libre-SOC&#x27;s.20SimpleV.html#211713430">(Sep 30 2020 at 04:07)</a>:</h4>
<p>That's cool!</p>
<p>Right now we're mostly planning on aiming at a "common denominator" approach with the portable simd stuff. It feels like specific support for SimpleV might end up in <code>core::arch</code> instead of <code>core::simd</code>.</p>



<a name="211714507"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Libre-SOC%27s%20SimpleV/near/211714507" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jacob Lifshay <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Libre-SOC&#x27;s.20SimpleV.html#211714507">(Sep 30 2020 at 04:31)</a>:</h4>
<p>I was mostly expecting that, though supporting all the different sizes of fixed-length vectors could definitely go in <code>core::simd</code>, potentially as a future extension. SimpleV will support vectorized versions of some operations that are usually scalar-only, such as integer division or remainder. It may also support instructions for sin, cos, exp, and others, with the option to switch between faster, less-accurate versions, and slower, completely accurate versions.</p>



<a name="211718662"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Libre-SOC%27s%20SimpleV/near/211718662" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Lokathor <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Libre-SOC&#x27;s.20SimpleV.html#211718662">(Sep 30 2020 at 05:57)</a>:</h4>
<p>Currently we're aiming at having types for 64, 128, 256, and 512 bit SIMD vectors, with a lane count based on the element type involved.</p>
<p>But, the functions available will be "most everything", even if it's not available in specific hardware (LLVM will fallback to scalar processing as necessary). So if someone <em>does</em> compile their <code>core::simd</code> code that contains integer divisions for SimpleV then LLVM should automatically select the correct instructions when the support is there.</p>
<p>The final part, about options to trade between accuracy and speed, that I'm not sure about. There have been similar proposals before and there was some strong pushback. People are extremely picky about their floats. If it was separate methods that might be fine, but since most platforms don't support that concept as much it might be thrown in the <code>core::arch</code> pile.</p>



<a name="211720062"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Libre-SOC%27s%20SimpleV/near/211720062" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jubilee <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Libre-SOC&#x27;s.20SimpleV.html#211720062">(Sep 30 2020 at 06:23)</a>:</h4>
<p>A lot of operations for vectorization are specific to the ability to load multiple values into vector registers and then do various kinds of permutations on them, which has been a design concern and subject of API debate for <code>core::simd</code>, and some of our users are definitely not satisfied without that. I'm quite happy to see people using the Open Power ISA, and your project seems pretty interesting, but I thought I'd give you a heads up that there's a reason we are implementing a very different style of vector programming: explicit and type-oriented, not "pragma"-oriented.</p>



<a name="211721301"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Libre-SOC%27s%20SimpleV/near/211721301" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jacob Lifshay <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Libre-SOC&#x27;s.20SimpleV.html#211721301">(Sep 30 2020 at 06:45)</a>:</h4>
<p>I personally prefer explicit vectorization over pragmas any day (though automatic optimizations are also nice), so I completely understand. Do note that SimpleV is mostly being designed as a target for GPU shaders, which are all written using SIMT. We are also thinking about having hardware support for vectors of short vectors, such as <code>[[f32; 3]; 16]</code>, where each <code>[f32; 3]</code> subvector would be enabled or disabled by a single predicate bit as a group -- the type of the mask would be <code>mask1x16</code> or equivalent.</p>



<a name="211721503"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Libre-SOC%27s%20SimpleV/near/211721503" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jubilee <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Libre-SOC&#x27;s.20SimpleV.html#211721503">(Sep 30 2020 at 06:48)</a>:</h4>
<p>SimpleV does seem to have its own niche, yes!<br>
I must admit I have not written a shader before so I have no familiarity with the limitations of shader code yet except through the abstract understanding that it uses SIMT and limits data dependencies. No shuffles in that world, huh?</p>



<a name="211723065"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Libre-SOC%27s%20SimpleV/near/211723065" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jubilee <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Libre-SOC&#x27;s.20SimpleV.html#211723065">(Sep 30 2020 at 07:12)</a>:</h4>
<p>Also if this is going to be based on Power ISA, how does it mesh (or not, as the case may be) with the existing AltiVec story?</p>



<a name="211855936"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Libre-SOC%27s%20SimpleV/near/211855936" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jacob Lifshay <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Libre-SOC&#x27;s.20SimpleV.html#211855936">(Oct 01 2020 at 00:16)</a>:</h4>
<p><span class="user-mention silent" data-user-id="281757">Jubilee</span> <a href="#narrow/stream/257879-project-portable-simd/topic/Libre-SOC's.20SimpleV/near/211721503">said</a>:</p>
<blockquote>
<p>SimpleV does seem to have its own niche, yes!<br>
I must admit I have not written a shader before so I have no familiarity with the limitations of shader code yet except through the abstract understanding that it uses SIMT and limits data dependencies. No shuffles in that world, huh?</p>
</blockquote>
<p>Actually you can have shuffles and other inter-lane operations, they're generally referred to as subgroup operations in Vulkan's lingo.</p>



<a name="211856037"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Libre-SOC%27s%20SimpleV/near/211856037" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jubilee <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Libre-SOC&#x27;s.20SimpleV.html#211856037">(Oct 01 2020 at 00:18)</a>:</h4>
<p>Ahhh.</p>



<a name="211856653"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Libre-SOC%27s%20SimpleV/near/211856653" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jacob Lifshay <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Libre-SOC&#x27;s.20SimpleV.html#211856653">(Oct 01 2020 at 00:28)</a>:</h4>
<p><span class="user-mention silent" data-user-id="281757">Jubilee</span> <a href="#narrow/stream/257879-project-portable-simd/topic/Libre-SOC's.20SimpleV/near/211723065">said</a>:</p>
<blockquote>
<p>Also if this is going to be based on Power ISA, how does it mesh (or not, as the case may be) with the existing AltiVec story?</p>
</blockquote>
<p>We have not completely decided yet, I was thinking we would have the VSX (AltiVec + FP) registers be shared with SimpleV's FP registers -- other than that, AltiVec and SimpleV would most likely be independent extensions. SimpleV is planned to have 128 64-bit integer registers and 128 64-bit FP registers both of which extend the scalar register set. Vector instructions would have their inputs and outputs be ranges of consecutive registers where the registers' backing storage is essentially bitcasted to the operand and result types.</p>



<a name="211857466"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Libre-SOC%27s%20SimpleV/near/211857466" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jubilee <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Libre-SOC&#x27;s.20SimpleV.html#211857466">(Oct 01 2020 at 00:41)</a>:</h4>
<p>nod</p>



<a name="212350807"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Libre-SOC%27s%20SimpleV/near/212350807" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jubilee <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Libre-SOC&#x27;s.20SimpleV.html#212350807">(Oct 05 2020 at 20:15)</a>:</h4>
<p><del>Oh wait, I misread something. Consistently. For a week or two. Again.</del></p>



<a name="213660916"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/257879-project-portable-simd/topic/Libre-SOC%27s%20SimpleV/near/213660916" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Cole Poirier <a href="https://rust-lang.github.io/zulip_archive/stream/257879-project-portable-simd/topic/Libre-SOC&#x27;s.20SimpleV.html#213660916">(Oct 17 2020 at 17:07)</a>:</h4>
<p><span class="user-mention silent" data-user-id="281757">Jubilee</span> <a href="#narrow/stream/257879-project-portable-simd/topic/Libre-SOC's.20SimpleV/near/212350807">said</a>:</p>
<blockquote>
<p><del>Oh wait, I misread something. Consistently. For a week or two. Again.</del></p>
</blockquote>
<p>If you have any questions please ask. Jacob explained a significant part of his Vulkan software renderer/driver/shader compiler to me when I asked. SimpleV to me as a novice seems like a much more ergonomic way to do simd. I work with Jacob on the SOC project that he is building Kazan for. The project is being funded via NLNET Privacy and Enhanced Trust grants. I know Jacob is excited about the rust portable simd and wants to collaborate on adding support for simplev so yeah if you want more information or explanation of it please ask him :)</p>



<hr><p>Last updated: Aug 07 2021 at 22:04 UTC</p>
</html>